1. Field of the Invention
The present invention relates to semiconductor electronic devices, and, more particularly, to formation of self-aligned doped regions in gallium arsenide and related devices.
2. Description of the Related Art.
Gallium arsenide has emerged as a leading contender for high speed integrated circuits because of its high electron mobility. Further, it is available in semi-insulating form and most gallium arsenide device technologies are expected to have better radiation hardness for total dose ionizing radiation than silicon. The gallium arsenide junction field effect transistor (JFET) in particular is expected to have higher hardness for single event upset when used in complementary integrated circuit design. The direct coupled FET logic (DCFL) based on enhancement/depletion technology has emerged as the major candidate for low power, high speed integrated circuit applications. But the enhancement mode (normally-off) MESFET fabricated by the recessed gate process needs severe process control due to the threshold voltage adjustment by wet or dry etching and suffers from a yield loss problem because of the recess etch. In the planar process, enhancement mode MESFET (whether self-aligned or not) threshold voltage cannot be adjusted after the channel regions are formed; thus the threshold voltage must be controlled by carefully screening the starting material and improving the reproducibility of the ion-implantation and annealing steps.
In contrast, JFET processes offer more fabrication flexibility without any loss of device performance and with the advantage of larger logic swing in integrated circuits. In known JFET processes (see, for example, Y. Kato et al, High Speed and Low Power GaAs JFET Technology, 1982 GaAs IC Symposium, 187-190) the p+ junction gate regions are formed by selective diffusion using a gaseous diffusion source or other solid sources that must be subsequently stripped off. Thus micron sized gates cannot be fabricated as the gate metal has to be realigned to the p+ region. The same reasoning applies to ion-implanted junctions; see R. Zuleeg et al, Double Implanted GaAs Complementary JFETs, 5 IEEE Elec.Dev.Lett. 21 (1984). This realignment problem also requires the source and drain be placed far from the gate to allow for alignment tolerances and thus introduces series resistances. Also, the threshold voltage cannot be adjusted after the fabrication is complete because the ohmic contacts degrade under high temperature treatment. And thus the known JFET processes have the problems of unavailability of micron sized gates and lack of threshold voltage adjustment.
Bipolar aluminum gallium arsenide heterojunction transistors, especially as used in heterojunction I.sup.2 L devices (see, H. Yuan, GaAs Bipolar Gate Array Technology, 1982 GaAs IC Symposium 100), are limited in speed by device size. Typical processes use implants such as Be to form p+ regions which then have gold-zinc ohmic contacts applied, but this requires alignment of the contact after the implant and limits size reduction. It is a problem to achieve self-aligned contacts in gallium arsenide and other III-V devices.